FIG. 1 shows a semiconductor memory 100 with a memory cell array 40. The memory cell array comprises memory cells which are designed as DRAM (dynamic random access memory) cells, for example. For the sake of simplicity, only one memory cell comprising a storage capacitor SC and a selection transistor AT is illustrated in the memory cell array 40. The control terminal of the selection transistor AT is connected to a wordline WL. The storage capacitor SC is connected to a terminal for application of a reference potential, and is also connected to a bitline BL via the controllable path of the selection transistor.
Read or write accesses are controlled synchronously with an external clock signal CLKE, applied to a clock terminal T100. A clock receiver circuit 20 receives the external clock signal CLKE and generates an internal clock signal CLKI. Internal procedures such as activating the memory cell SZ by turning on and off the selection transistor AT are operated synchronously with the internal clock signal CLKI.
For the read access to a memory cell, a read command RD is externally applied to a control terminal S100b connected to a control circuit 10. As a result, the memory cell SZ is activated for a read access, and a data item DQ stored in the memory cell SZ is supplied to an output circuit 50 for buffering. After having received read command RD, control circuit 10 generates an internal read command signal PAR synchronous with rising and falling edges of the internal clock signal CLKI. The internal read command signal PAR is transmitted to a latency counter circuit 30. After a delay time which is determined depending on a configuration signal MR applied to a control terminal S100a, latency counter circuit 30 generates a time-shifted internal read command signal OUT synchronous with the internal clock signal CLKI. The time-shifted internal read command signal OUT actuates output circuit 50. As a result, output circuit 50 is enabled to output the buffered data item DQ to a data terminal 10100.
Due to internal delay and processing times of the output circuit 50, which are mainly effected by a data path delay time tDp and an off-chip driver delay time tOCD of the output circuit, the data item DQ does not appear simultaneously with the instant the external read command RD is applied to control terminal S100b. In order to avoid data items being generated at the data terminal 10100 at arbitrary points in time after the external read command RD has been applied to control terminal S100b, the latency between applying the external read command RD and the instant when the appropriate data item appears at the data terminal IO100 is set to a predetermined value depending on configuration signal MR. The latency is usually specified by the so-called CAS latency.
Instead of using a single internal clock signal CLKI, a modern SDRAM (synchronous dynamic random access memory) device runs in different clock domains. Clock receiver 20 of FIG. 1, for example, is applied by an external clock signal and generates a system clock signal CLKD which is delayed with regard to the external clock signal CLKE. A DLL (delay lock loop) circuit is connected to the clock receiver circuit for generating a DLL clock signal, DLLCLK, with a constant lead time to the system clock signal CLKD. The internal read command signal PAR is, for example, generated by the control circuit 10, synchronous with the system clock signal CLKD, whereas the time-shifted internal read command signal OUT is generated by the latency counter circuit 30, synchronous with the DLL clock signal DLLCLK.
FIG. 2 shows the relation between the clock signals CLKE, CLKD and DLLCLK. The system clock signal CLKD is delayed with regard to the external clock signal CLKE by a clock receiver delay time tRCV including subsequent driver delay times. The DLL clock signal DLLCLK runs “in advance” of the system clock signal CLKD. A time shift tA between the two clock signals CLKD and DLLCLK is equal to the sum of delay times tRCV, tDp and tOCD. This relation is maintained by the DLL circuit and is valid anytime the DLL circuit is locked and the clocks are not switched, as for example when the integrated memory is operated in a power down mode causing discontinuities of the clock signals. The time shift tA of the DLL clock signal DLLCLK is chosen such that the data item DQ, which is internally triggered by the DLL clock signal DLLCLK, appears externally aligned to the marked edge of the external clock signal CLKE when output circuit 50 is actuated by the time-shifted internal read command signal OUT, at the marked edge of DLL clock signal DLLCLK.
The time shift tA changes with temperature and supply voltage. However, the DLL circuit iteratively adjusts the DLL clock signal DLLCLK to the system clock signal CLKD. As illustrated in FIG. 2, the DLL clock signal DLLCLK runs “in advance” of the external clock signal CLKE and the internal clock signal CLKD. The marked rising edges of the external clock signal CLKE, the system clock signal CLKD and the DLL clock signal DLLCLK correspond to each other such that the marked rising edge of the system clock signal CLKD is generated by clock receiver circuit 20 with the delay time tRCV when the corresponding edge of the external clock signal CLKE actuates the clock receiver circuit 20. Furthermore, if the output circuit 50 is enabled at the marked rising edge of the DLL clock signal DLLCLK, a data item buffered in output circuit 50 appears at the data terminal IO100 at the rising edge of external clock signal CLKE. In the example shown in FIG. 2, the DLL circuit generates the DLL clock signal such that a corresponding edge of the DLL clock signal DLLCLK runs “in advance” of the corresponding edge of the system clock signal CLKD by a time shift tA of 1.5 clock cycles.
FIG. 3A shows the two clock signals CLKD and DLLCLK. The DLL clock signal DLLCLK runs “in advance” of the system clock signal CLKD. The internal read command signal PAR is generated in a system clock domain, whereas the time-shifted internal read command signal OUT is generated in a DLL clock domain. If a data signal appears at data terminal IO100 when the marked rising edge ECO of the system clock signal CLKD is valid, the time-shifted internal read command signal OUT is valid at the marked rising edge ED0 of the DLL clock signal DLLCLK, which is 1.5 clock cycles ahead of the marked rising edge ECO of the system clock signal CLKD. However, this is not possible because the time-shifted internal read command signal OUT is generated after the latency counter circuit 30 is actuated by the internal read command signal PAR. If the internal read command signal PAR is generated at the marked rising edge ECO of the system clock signal CLKD, the marked rising edge ED0 of the time-shifted clock signal DLLCLK has passed 1.5 clock cycles in advance. This means, with the clock constellation shown in FIG. 3A, the time-shifted internal read command signal OUT is generated by the latency counter circuit 30 with a target delay of at least two clock cycles tCK with regard to the clock cycle of the marked edge ED0 of the DLL clock signal DLLCLK.
FIG. 3B shows the system clock signal CLKD and the DLL clock signal DLLCLK with a higher frequency than the clock signals shown in FIG. 3A. The time shift tA is the same as the one shown in FIG. 3A, because the time shift is dependent only on the constant parameters of the data path delay time tDP, off-chip driver delay time tOCD and clock receiver delay time tRCV. Due to the higher frequency, the corresponding edges EC0 and ED0 of the system clock signal CLKD and the DLL clock signal DLLCLK are time-shifted with regard to one another by about three clock cycles. If the internal read command signal PAR is valid at the marked edge ECO of system clock signal CLKD, the time-shifted internal read command signal OUT is generated at the rising edges ED3, ED4, . . . , EDm, which are delayed by 3, 4, . . . , m clock cycles tCK with regard to the marked rising edge 0 of the DLL clock signal DLLCLK.
With very low clock frequencies, as shown in FIG. 3C, the internal read command signal PAR is generated and triggered with the marked rising edge ECO of system clock signal CLKD a long time ahead of the rising edge ED1 of the DLL clock signal DLLCLK, but after the marked rising edge ED0 of the DLL clock signal DLLCLK.
The number of clock cycles tCK between the marked edge ED0 and the edge of the DLL clock signal DLLCLK at which the time-shifted internal read command signal OUT is generated is dependent on the configuration signal MR. The CAS latency is a value which indicates the number of clock cycles between the point in time when the external read command signal RD is applied to control terminal S100b to start a read access to a memory cell and the point in time when the data item DQ of this memory cell appears at data terminal IO100. One clock cycle before the data is driven out, a preamble for a data strobe signal is activated. For this reason, the time-shifted internal read command signal OUT is synchronized with a rising edge of the DLL clock signal DLLCLK, which is one clock cycle tCK earlier than the value of the CAS latency indicates.
FIG. 3A shows the constellation wherein the time shifted internal read command signal OUT is synchronized with the rising edge ED2 of the DLL clock signal DLLCLK, which is two clock cycles tCK after the marked rising edge ED1 of the DLL clock signal DLLCLK. The CAS latency for this constellation equals 3.
In FIG. 3B, the minimum possible target delay is three clock cycles tCK later than the marked rising edge ED0 of the DLL clock signal DLLCLK. The CAS latency for this constellation equals 4.
In FIG. 3C, the time-shifted internal read command signal OUT is synchronized with the first rising edge ED1 of the DLL clock signal DLLCLK following the rising edge ED0. The CAS latency for this clock constellation equals 2.
FIG. 4 shows an embodiment used in a Graphic DRAM to synchronize the time shifted internal read command signal OUT derived from the internal read command signal PAR with one of the rising edges of the DLL clock signal DLLCLK. The shift between rising edge ED0 of the DLL clock signal DLLCLK and the edge with which the time shifted internal read command signal OUT is synchronized is given by the configuration signal MR which is supplied to a latency counter circuit 30′. A clock generating circuit 20′ comprises a clock receiver 21′, a DLL circuit 22′ and a DLL feedback delay circuit 23′. The clock receiver circuit 21′ is supplied with the external clock signal CLKE and generates the system clock signal CLKD, which is time-shifted by the DLL circuit 22′ and produced, in the DLL clock domain, as DLL clock signal DLLCLK. The DLL clock signal DLLCLK is driven to the latency counter circuit 30′. The latency counter circuit 30′ is also driven by a clock signal PARCLK, which is generated by the DLL feedback delay circuit 23′. The clock signal PARCLK is a clock signal delayed with regard to the DLL clock signal DLLCLK by 4–6 ns and a margin of 0.5 clock cycles of the DLL clock signal DLLCLK.
The latency counter circuit 30′ includes an input counter circuit 31′ and an output counter circuit 32′. The output counter circuit 32a′ is connected, via a shift register 32b′, to a latch circuit 33′ comprising FIFO (first-in-first-out) latching cells. The shift register 32b′ is driven by a control signal derived from the configuration signal MR by a latency decoder 34′. A control signal iPoint′ is generated synchronously with the delayed clock signal PARCLK. A control signal oPoint′ is generated synchronously with the DLL clock signal DLLCLK. Depending on a state of the control signal iPoint′ the internal read command signal PAR is latched into one of the FIFO latching cells of the latch circuit 33′. The internal read command signal PAR is released from one of the FIFO latching cells depending on the state of the control signal oPoint′. The shift generated in the shift register 32b′ determines the number of clock cycles by which the time shifted internal read command signal OUT is delayed in relation to the internal read command signal PAR.
In the described solution for a graphic DRAM, the control signals iPoint′ and oPoint′ are aligned once just after the DLL circuit 22′ is locked. The alignment is accomplished by an initialization sequence in an initialization phase of the integrated memory. After termination of the initialization sequence, the integrated memory is switched into a normal operation mode for read or write access. In the normal operation mode, all clock switching is carried out such that control signals iPoint′ and oPoint′ are kept aligned. However, misaligned control signals remain stable until the next reset of the DLL circuit. Intermediate resets are not possible. This means that the solution usually applied for graphic DRAMs does not allow a self-adjustment of the control signals iPoint′ and oPoint′.
Furthermore, problems occur during a fast recovery of the state of the control signals iPoint′ and oPoint′ after a power down exit. The clock signal PARCLK, synchronized with the control signal iPoint′, is derived from the DLL clock signal DLLCLK and delayed with regard to the DLL clock signal DLLCLK by several clock cycles tCK. Due to a very tight timing budget after a power down exit, there may be no clock signal PARCLK available for latching an early internal read command signal PAR.
A further method for synchronizing the internal read command signal PAR with the DLL clock signal DLLCLK is used in commodity DRAMs. In this case, several clock signals derived from the DLL clock signal DLLCLK are generated with different delay times. The internal read command signal PAR is latched synchronously with the different delayed clock signals, until it is latched synchronously with the DLL clock signal DLLCLK. However, due to the high operation frequency in a modern DRAM, the large number of differently delayed clock signals required to ensure a reliable synchronization is no longer available. Therefore, integrated semiconductor memories using such a solution for synchronization are operated at low frequencies.